tag:blogger.com,1999:blog-3262721394189427874.post7206873540083102431..comments2012-01-24T14:12:45.432-08:00Comments on TRIGR User Blog: TRIGR Teamhttp://www.blogger.com/profile/11564334398210117228noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-3262721394189427874.post-5324394220457316092012-01-24T14:12:45.432-08:002012-01-24T14:12:45.432-08:00Hey All,
We have had a TRIGR box for almost 2 ye...Hey All, <br /><br />We have had a TRIGR box for almost 2 years now! We have taken it many places and collected loads of data. We really do love this front end. I am currently developing VHDL IP that interfaces to the ADC inside the front end so we can bring samples into our processor. There are two main jobs ahead of me, first is the development of the SPI interface to command the ADC to output training sequences, etc. The second job is to perform an eye pattern calibration on that training sequence. I have a AD92XX 8-ch ADC LVDS Receiver that brings the samples and SPI interface into our FPGA through the EXP bus. However I don't know which nets are used in the EXP interface for Samples and which for SPI? I suppose I could just test them all (yuk!). Does anyone have any insight? I plan to release my finished code back to the community so any help may also help you! Thanks :)cosgromahttps://www.blogger.com/profile/11553891693455844907noreply@blogger.comtag:blogger.com,1999:blog-3262721394189427874.post-27306994786237220942012-01-24T12:26:24.801-08:002012-01-24T12:26:24.801-08:00This comment has been removed by the author.cosgromahttps://www.blogger.com/profile/11553891693455844907noreply@blogger.com